address instruction in Germany

address instruction [ədresinstrʌkʃən] adressenloser Befehl

Sentence patterns related to "address instruction"

1. The instruction cache system also includes a means for address translation which is responsive to an address translation invalidate instruction and a control logic circuit.

2. At least one predetermined bit of the instruction fetch address is used to select between the instruction sets.

3. The CPU sends a pointer address via the first address bus to the instruction mapping circuit.

4. Memory address where each instruction is located. For native applications, this is the actual memory address.

5. A further attribute may indicate that the fetch address is an even address in the instruction cache.

6. The address parts of BELL instructions may have three different meanings: address of a variable, address of an instruction, or constant.

Die Adreßteile von BELL-Befehlen können dreierlei Bedeutung haben: Adresse einer Variablen, Adresse eines Befehls oder Konstante.

7. If so, the instruction mapping circuit maps the pointer address to an address within the data cache.

8. Identifying the instruction to be fetched may include identifying an address stored in a program address pointer.

9. The data processing device has an instruction flow control unit that updates instruction addresses according the position dependent address steps.

10. The stored substitute address field may be adjusted after generating each instruction.

11. Device for assigning an instruction address coded to an electronic address recognition circuit, and for marking said circuit

12. Each byte offset identifies a memory address used by a machine code instruction.

13. If not, the pointer address is routed through the instruction mapping circuit unchanged.

14. An advanced load address table (ALAT) tracks status information for the advanced load instruction.

15. In this case, the absolute address of the data is derived from the absolute address of the instruction, thus avoiding address translation for the data.

16. 26 Each byte offset identifies a memory address used by a machine code instruction.

17. The control logic circuit is configured to invalidate an entry in the virtually tagged instruction cache in response to the address translation invalidate instruction.

18. Taking our hypothetical application with the 15000 byte virtual address space, assume that the application's first instruction accesses data stored at address 12374.

19. An address of program instruction data is placed in a word register and a mode register.

20. If a jump instruction was executed, the program counter will be modified to contain the address of the instruction that was jumped to and program execution continues normally.

21. The effective address of the access instruction is used without address translation to determine whether the level one cache for the processor core includes the data corresponding to the effective address.

22. The LK bit specifies whether the address of the next sequential instruction is saved in the Link Register as a return address for a subroutine call.

23. whether there is a current “in-care-of” address or “hold mail” instruction for the Account Holder; and

24. At the discretion of an instruction from its finite state machine's TABLE, the machine derives a "target" register's address either (i) directly from the instruction itself, or (ii) indirectly from the contents (e.g. number, label) of the "pointer" register specified in the instruction.

25. A first address generator generates a sequence of consecutive addresses and a second address generator (AG) generates a sequence of addresses that represents interleaving instruction ($g(a)(i)).

Ein erster Adressgenerator erzeugt eine Sequenz fortlaufender Adressen und ein zweiter Adressgenerator (AG) erzeugt eine die Verschachtelungsvorschrift (a(i)) repräsentierende Sequenz von Adressen.