1. A dual function adder for computing a hardware prefetch address and an arithmetic operation value

2. The system schedules explicit prefetch instructions into the critical section in advance of associated memory operations.

3. The core has enhancements to the K7's TLB architecture and added a hardware data prefetch mechanism to take better advantage of available memory bandwidth.

4. The IOMMU (26) comprises one or more caches (30), and is configured to read translation data from the I/O translation tables (36) responsive to a prefetch command (148) that specifies a first virtual address.