1. A frequency divider using a clock source with a plurality of phase signals of a multi-phase oscillator.

2. It is characterized by the fact that the adjustable frequency divider (4) rates a preferably constant frequency (f¿o?)

3. The PLL includes a phase frequency detector, a charge pump, a low pass filter, a voltage controlled oscillator and a frequency divider .

4. The low-power frequency divider generates a frequency-divided signal with frequency equal to the frequency of the input signal divided by a fixed ratio, and is equipped with a phase-voltage converter, a comparator, a phase-locked loop and a reset circuit.

5. Said phase-lock loop comprises a frequency adjusting arrangement (13) comprising a first and a second control input (1, 2), a first output which is connected to the frequency divider (9) and is used to generate a digital regulating signal, and a second output which is coupled to the controlled oscillator (8) and is used to generate an analog control signal.